A digital to analog converter (DAC) converts a digital input word to an analog output. Signal processors which utilize DACs typically operate in either a unipolar or bipolar mode, both of which will be briefly described below.
The generic equation for determining V.sub.OUT in unipolar and bipolar signal processor is shown in Equation 1: ##EQU1##
where MAX INPUT CODE is the maximum value of INPUT CODE or 2.sup.n -1, when INPUT CODE is an n-bit digital word, G is the gain of the signal processor and K1 and K2 are constants that determine the configuration mode. In the unipolar mode configuration (e.g., when the output voltage varies from 0 volts to 5 volts K1=1 and K2=0 so that V.sub.OUT varies between 0 and .vertline.G*V.sub.REF.vertline.. In the bipolar mode configuration (e.g., output voltage varies from -5 volts to 5 volts), K1=2 and K2=1 so that V.sub.OUT varies between .+-.G*V.sub.REF.
FIG. 1 shows an example of a previously known unipolar signal processor 10, which receives an input voltage V.sub.REF, control signal UPDATE and INPUT CODE, and generates analog output V.sub.OUT. INPUT CODE typically is an n-bit digital word that signal processor 10 uses to convert digital input voltage V.sub.REF to analog output V.sub.OUT. UPDATE is a binary input signal which determines when the INPUT CODE can be used to convert V.sub.REF to produce a new V.sub.OUT. When UPDATE is LOW, V.sub.OUT remains substantially constant. When UPDATE changes from LOW to HIGH, DAC 10 converts V.sub.REF to analog output V.sub.OUT based on the INPUT CODE.
Signal processor 10 includes current converter (DAC) stage 12, op-amp 22, capacitor 24 feedback resistor 20 and switch-resistance compensation element S.sub.F. Current converter stage 12 includes R-2R ladder 14, switches 16.sub.1 to 16.sub.n and latch and decoder 18 and switch-resistance compensation element S.sub.T.
The R-2R ladder 14 is coupled between V.sub.REF and switches 16.sub.1 to 16.sub.n, and includes n branches each containing a resistor 25.sub.i and a termination branch having resistor 27 and switch-resistance compensation element S.sub.T. The R-2R ladder 14 includes a resistor 23 between the top nodes of each branch. Typically, resistors 25 are twice as large as resistors 23. Termination branch resistor 27 is of the same value as resistors 25.sub.i. Switch-resistance compensation element S.sub.T of the termination branch is connected to GROUND. Resistor 27 and switch-resistance compensation element S.sub.T of the termination branch serve to balance the impedance of the R-2R ladder 14 at each top node. Without the termination branch, the current flowing through each branch would differ and thereby cause errors in the current conversion process.
The INPUT CODE in combination with the reference voltage causes an intermediate current, I.sub.DAC to flow according to Equation 2, R is the input impedance of the R-2R ladder: ##EQU2##
Feedback resistor 20, feedback switch-resistance compensation element S.sub.F,op-amp 22 and capacitor 24 form a current to voltage converter. The op-amp 22 has an inverting input (-) coupled to current converter 12, feedback resistor 20 and capacitor 24, a non-inverting input (+) coupled to GROUND, and an output coupled to V.sub.OUT. Capacitor 24 is coupled between inverting input (-) and V.sub.OUT to provide a first feedback loop around the op-amp 22. This first feedback loop is not required for operation. Feedback resistor 20 and switch-resistance element S.sub.F are coupled between inverting input (-) and V.sub.OUT to provide a second feedback loop around the op-amp 22. Switch-resistance compensation element S.sub.F,like switch-resistance compensation element S.sub.T,is required for matching of the on-resistance of switches 16.sub.i, from the R-2R ladder 14.
The current to voltage converter operates to convert intermediate current I.sub.DAC to the output voltage V.sub.OUT. The resulting, V.sub.OUT is shown in Equation 3: ##EQU3##
FIG. 2 shows a bipolar signal processor 30 which includes circuit 14, comprising an inverting amplifier 40 and gain resistors 42 and 44 coupled between V.sub.REF, and current converter 12. Amplifier 40 and gain resistors 42 and 44 serve to invert input voltage V.sub.REF. Inverted V.sub.REF (i.e., -V.sub.REF) is used to generate I.sub.REF, as described above in FIG. 1. Alternatively, amplifier 40 and resistors 42 and 44 could be located external to signal processor 30 in the signal path.
V.sub.REF is also coupled to level resistor 38, which is then coupled to the inverting input of op-amp 22 via switch-resistance compensation element S.sub.O. Capacitor 24 and feedback resistor 36 are coupled between inverting input (-) and V.sub.OUT, to provide first and second feedback loops, respectively, around op-amp 22. This is one technique for applying opposite polarity to the current converter and to the level circuitry, a condition which is required for operation of the DAC. However, other suitable techniques for establishing this condition are well-known in the art. Switch-resistance compensation elements S.sub.O and S.sub.F are included in the circuit to match the impedance of the switches in the R-2R ladder 14 described above in FIG. 1.
A first signal path from V.sub.REF to V.sub.OUT via level resistor 38, feedback resistor 36 and op-amp 22, inverts the input signal V.sub.REF at V.sub.OUT. A second signal path from V.sub.REF to V.sub.OUT via gain resistors 42, 44, inverting amplifier 40, current converter 12 and op-amp 22, produces the voltage shown in Equation 4 at V.sub.OUT :
V=-I.sub.DAC* 2R (4)
where I.sub.DAC is defined by Equation 2. The total output voltage at V.sub.OUT is the combination of the voltage from the first and second signal paths and is shown in Equation 5: ##EQU4##
Equation 5 equals the desired result of the voltage conversion shown in Equation 1 for a bipolar configuration where K1=2, K2=1 and G=1. Thus, for a 10 volt input (V.sub.REF =10) , the first signal path yields a voltage of -10 volts, while the second signal path provides a voltage between 0 and 20 volts based on the INPUT CODE so that V.sub.OUT has a range of .+-.10 volts.
The prior art consists of various configurations of signal processor 10 and/or signal processor 30 from FIGS. 1 and 2 in monolithic or discrete form. The configuration was typically chosen to be unipolar or bipolar only and connected permanently as such. To make the configuration switchable between unipolar and bipolar modes, however, extra discrete switches and operational amplifiers have been added, as shown in FIG. 3.
In FIG.3, non-inverting amplifier 52 and switch 56 are connected to the signal processor 30 from FIG. 2. Amplifier 52 has inverting input (-) and its output coupled to resistor 38 and noninverting input (+) coupled to switch 56. Switch 56 is provided to couple noninverting input (+) to either V.sub.REF or V.sub.OUT based on an external logic signal. The signal processor in FIG. 3 operates in unipolar mode when switch 56 connects noninverting input(+) of amplifier 52 to V.sub.OUT and operates in bipolar mode when switch 56 connects noninverting input (+) of amplifier 52 to V.sub.REF. Otherwise the signal processor in FIG. 3 operates in essentially the same manner as those described above in FIGS. 1 and 2 based on the selected mode. The additional external op-amp 52 (and switch 56) adds an offset and, as such, may provide less than optimum dc performance of the signal processor.
Additionally, the ac performance of the signal processor is not optimum due to the finite bandwidth and slew rate of this op amp. A specific implementation of the circuit shown in FIG. 3 is shown in the data sheet for LTC 1597 produced by Linear Technology Corporation of Milpitas, California.